No WMI_READY with SDIO card

Topics: Developer Forum
Jul 27, 2009 at 11:09 AM

Hi,

I have built the cewifidriverar6000-21374 driver sources and am running
them with a CardAccess SDIO SDG10A on a TI board (DaVinci variant).
CardAccess kindly flashed the card with the v1.1 firmware and the driver
confirms this:

4294927456 PID:400002 TID:5590012 BMI Get Target ID: Enter (device: 0xC1247C90)
4294927521 PID:400002 TID:5590012 BMI Get Target ID: Exit (ID: 0x11000044)
4294927521 PID:400002 TID:5590012 FIRMWARE MAJOR VERSION ==> 1
4294927524 PID:400002 TID:5590012 FIRMWARE MINOR VERSION ==> 1

The driver gets part way through initialisation but then a timeout
occurs waiting for the "WMI_READY event". I enabled some logging but
cannot see any failures. Read/write commands and card interrupts all
appear to be handled successfully (apologies for the long log):

4294928069 PID:400002 TID:5590012 HTCStart Enter
4294928071 PID:400002 TID:5590012 SDHC SendCommand: Cmd:0x34 Arg:0x80000803
4294928072 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3403100000]
4294928074 PID:400002 TID:5590012 HIFReadWrite:Enter
4294928076 PID:400002 TID:5590012 Address 0x418
4294928077 PID:400002 TID:5590012 Byte mode (BlockLen: 4, BlockCount: 1)
4294928083 PID:400002 TID:5590012 SDHC SendCommand: Cmd:0x35 Arg:0x94083004
4294928085 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294928085 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Sent 4 bytes [df0003ff]
4294928089 PID:400002 TID:36a0002 SDHC SendCommand: Cmd:0x34 Arg:0x00000A00
4294928091 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3402100000]
4294928091 PID:400002 TID:36a0002 hifIRQHandler : Enter
4294928092 PID:400002 TID:36a0002 htcInterruptDisabler Enter target: 0xD1231250
4294928092 PID:400002 TID:36a0002 htcInterruptPending Enter target: 0xD1231250
4294928092 PID:400002 TID:36a0002 HIFReadWrite:Enter
4294928092 PID:400002 TID:36a0002 Address 0x400
4294928092 PID:400002 TID:36a0002 Byte mode (BlockLen: 1, BlockCount: 1)
4294928094 PID:400002 TID:36a0002 SDHC SendCommand: Cmd:0x35 Arg:0x10080001
4294928098 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294928098 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Received 1 bytes [10]
4294928101 PID:400002 TID:36a0002 HIFReadWrite:Enter
4294928102 PID:400002 TID:36a0002 Address 0x418
4294928102 PID:400002 TID:36a0002 Byte mode (BlockLen: 1, BlockCount: 1)
4294928103 PID:400002 TID:36a0002 SDHC SendCommand: Cmd:0x35 Arg:0x10083001
4294928105 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294928105 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Received 1 bytes [df]
4294928108 PID:400002 TID:36a0002 HIFReadWrite:Enter
4294928108 PID:400002 TID:36a0002 Address 0x418
4294928109 PID:400002 TID:36a0002 Byte mode (BlockLen: 1, BlockCount: 1)
4294928110 PID:400002 TID:36a0002 SDHC SendCommand: Cmd:0x35 Arg:0x90083001
4294928111 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294928112 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Sent 1 bytes [00]
4294928114 PID:400002 TID:36a0002 htcInterruptDisabler: Exit
4294928114 PID:400002 TID:36a0002 htcDsrHandler: Enter (target: 0xD1231250
4294928114 PID:400002 TID:36a0002 HIFReadWrite:Enter
4294928114 PID:400002 TID:36a0002 Address 0x400
4294928114 PID:400002 TID:36a0002 Byte mode (BlockLen: 28, BlockCount: 1)
4294928115 PID:400002 TID:36a0002 SDHC SendCommand: Cmd:0x35 Arg:0x1408001C
4294928120 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294928120 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Received 28 bytes [100004f00e00000044000011a5ee6a1600023b0138809608000003ff]
4294928123 PID:400002 TID:36a0002 
<------- Register Table -------->
4294928124 PID:400002 TID:36a0002 Int Status: 0x10
4294928124 PID:400002 TID:36a0002 CPU Int Status: 0x0
4294928124 PID:400002 TID:36a0002 Error Int Status: 0x4
4294928124 PID:400002 TID:36a0002 Counter Int Status: 0xf0
4294928125 PID:400002 TID:36a0002 Mbox Frame: 0xe
4294928125 PID:400002 TID:36a0002 Rx Lookahead Valid: 0x0
4294928125 PID:400002 TID:36a0002 Rx Lookahead 0: 0x11000044
4294928125 PID:400002 TID:36a0002 Rx Lookahead 1: 0x166aeea5
4294928125 PID:400002 TID:36a0002 Rx Lookahead 2: 0x13b0200
4294928126 PID:400002 TID:36a0002 Rx Lookahead 3: 0x8968038
4294928126 PID:400002 TID:36a0002 Int Status Enable: 0x0
4294928126 PID:400002 TID:36a0002 Counter Int Status Enable: 0xff
4294928126 PID:400002 TID:36a0002 <------------------------------->
4294928127 PID:400002 TID:36a0002 Valid interrupt source(s) in INT_STATUS: 0x10
4294928127 PID:400002 TID:36a0002 Counter Interrupt
4294928127 PID:400002 TID:36a0002 Valid interrupt source(s) in COUNTER_INT_STATUS: 0xf0
4294928129 PID:400002 TID:36a0002 endPoint(0): D1231258
4294928129 PID:400002 TID:36a0002 endPoint(1): D123198C
4294928129 PID:400002 TID:36a0002 endPoint(2): D12320C0
4294928130 PID:400002 TID:36a0002 endPoint(3): D12327F4
4294928130 PID:400002 TID:36a0002 HIFReadWrite:Enter
4294928130 PID:400002 TID:36a0002 Address 0x41b
4294928130 PID:400002 TID:36a0002 Byte mode (BlockLen: 1, BlockCount: 1)
4294928131 PID:400002 TID:36a0002 SDHC SendCommand: Cmd:0x35 Arg:0x90083601
4294928132 PID:400002 TID:36a0002 Tx Credits Available: 1
4294928132 PID:400002 TID:36a0002 HIFReadWrite:Enter
4294928134 PID:400002 TID:36a0002 Address 0x450
4294928134 PID:400002 TID:36a0002 Byte mode (BlockLen: 1, BlockCount: 1)
4294928136 PID:400002 TID:36a0002 HIFReadWrite:Enter
4294928136 PID:400002 TID:36a0002 Address 0x800
4294928136 PID:400002 TID:36a0002 Byte mode (BlockLen: 4, BlockCount: 1)
4294928137 PID:400002 TID:36a0002 Mailbox(0), Block size: 1
4294928137 PID:400002 TID:36a0002 Tx Credits Available: 1
4294928137 PID:400002 TID:36a0002 HIFReadWrite:Enter
4294928139 PID:400002 TID:36a0002 Address 0x454
4294928139 PID:400002 TID:36a0002 Byte mode (BlockLen: 1, BlockCount: 1)
4294928141 PID:400002 TID:36a0002 HIFReadWrite:Enter
4294928141 PID:400002 TID:36a0002 Address 0x1000
4294928142 PID:400002 TID:36a0002 Byte mode (BlockLen: 4, BlockCount: 1)
4294928142 PID:400002 TID:36a0002 Mailbox(1), Block size: 128
4294928143 PID:400002 TID:36a0002 Tx Credits Available: 1
4294928144 PID:400002 TID:36a0002 HIFReadWrite:Enter
4294928145 PID:400002 TID:36a0002 Address 0x458
4294928145 PID:400002 TID:36a0002 Byte mode (BlockLen: 1, BlockCount: 1)
4294930153 PID:400002 TID:36a0002 HIFReadWrite:Enter
4294930153 PID:400002 TID:36a0002 Address 0x1800
4294930153 PID:400002 TID:36a0002 Byte mode (BlockLen: 4, BlockCount: 1)
4294930154 PID:400002 TID:36a0002 Mailbox(2), Block size: 128
4294930155 PID:400002 TID:36a0002 Tx Credits Available: 1
4294930157 PID:400002 TID:36a0002 HIFReadWrite:Enter
4294930157 PID:400002 TID:36a0002 Address 0x45c
4294930157 PID:400002 TID:36a0002 Byte mode (BlockLen: 1, BlockCount: 1)
4294930159 PID:400002 TID:36a0002 HIFReadWrite:Enter
4294930159 PID:400002 TID:36a0002 Address 0x2000
4294930159 PID:400002 TID:36a0002 Byte mode (BlockLen: 4, BlockCount: 1)
4294930160 PID:400002 TID:36a0002 Mailbox(3), Block size: 128
4294930162 PID:400002 TID:36a0002 htcDSRHandler: Exit
4294930162 PID:400002 TID:36a0002 hifIRQHandler : Exit
4294930166 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294930166 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Sent 1 bytes [0f]
4294930169 PID:400002 TID:36d0002 SDHC SendCommand: Cmd:0x35 Arg:0x1008A001
4294930170 PID:400002 TID:2a50002 htcRegCompletion - Enter
4294930170 PID:400002 TID:2a50002 COUNTER_INT_STATUS_DISABLE:0xff
4294930170 PID:400002 TID:2a50002 htcInterruptEnabler Enter target: 0xD1231250
4294930170 PID:400002 TID:2a50002 HIFReadWrite:Enter
4294930171 PID:400002 TID:2a50002 Address 0x418
4294930171 PID:400002 TID:2a50002 Byte mode (BlockLen: 1, BlockCount: 1)
4294932178 PID:400002 TID:2a50002 htcInterruptEnabler Exit
4294932179 PID:400002 TID:2a50002 htcDSRHandler - ACK
4294932179 PID:400002 TID:2a50002 htcRegCompletion - Exit
4294932181 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294932181 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Received 1 bytes [01]
4294932184 PID:400002 TID:36d0002 SDHC SendCommand: Cmd:0x35 Arg:0x941FF804
4294932185 PID:400002 TID:2a50002 htcRegCompletion - Enter
4294932185 PID:400002 TID:2a50002 TX_CREDIT_COUNTER_DECREMENT_REG
4294932185 PID:400002 TID:2a50002 Pulling 0 tx credits from the target
4294932185 PID:400002 TID:2a50002 HIFReadWrite:Enter
4294932186 PID:400002 TID:2a50002 Address 0x41b
4294932186 PID:400002 TID:2a50002 Byte mode (BlockLen: 1, BlockCount: 1)
4294932187 PID:400002 TID:2a50002 htcRegCompletion - Exit
4294932189 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294932189 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Sent 4 bytes [01000000]
4294932192 PID:400002 TID:36d0002 SDHC SendCommand: Cmd:0x35 Arg:0x1008A801
4294932194 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294932194 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Received 1 bytes [01]
4294932197 PID:400002 TID:36d0002 SDHC SendCommand: Cmd:0x35 Arg:0x942FF804
4294932197 PID:400002 TID:2a50002 htcRegCompletion - Enter
4294932198 PID:400002 TID:2a50002 TX_CREDIT_COUNTER_DECREMENT_REG
4294932198 PID:400002 TID:2a50002 Pulling 0 tx credits from the target
4294932198 PID:400002 TID:2a50002 HIFReadWrite:Enter
4294932198 PID:400002 TID:2a50002 Address 0x41b
4294932198 PID:400002 TID:2a50002 Byte mode (BlockLen: 1, BlockCount: 1)
4294932200 PID:400002 TID:2a50002 htcRegCompletion - Exit
4294932202 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294932203 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Sent 4 bytes [80000000]
4294932205 PID:400002 TID:36d0002 SDHC SendCommand: Cmd:0x35 Arg:0x1008B001
4294932207 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294932209 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Received 1 bytes [01]
4294932209 PID:400002 TID:36d0002 SDHC SendCommand: Cmd:0x35 Arg:0x943FF804
4294932211 PID:400002 TID:2a50002 htcRegCompletion - Enter
4294932211 PID:400002 TID:2a50002 TX_CREDIT_COUNTER_DECREMENT_REG
4294932212 PID:400002 TID:2a50002 Pulling 0 tx credits from the target
4294932212 PID:400002 TID:2a50002 HIFReadWrite:Enter
4294932212 PID:400002 TID:2a50002 Address 0x41b
4294932212 PID:400002 TID:2a50002 Byte mode (BlockLen: 1, BlockCount: 1)
4294932213 PID:400002 TID:2a50002 htcRegCompletion - Exit
4294932219 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294932219 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Sent 4 bytes [80000000]
4294932222 PID:400002 TID:36d0002 SDHC SendCommand: Cmd:0x35 Arg:0x1008B801
4294932224 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294932224 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Received 1 bytes [01]
4294932227 PID:400002 TID:36d0002 SDHC SendCommand: Cmd:0x35 Arg:0x944FF804
4294932227 PID:400002 TID:2a50002 htcRegCompletion - Enter
4294932228 PID:400002 TID:2a50002 TX_CREDIT_COUNTER_DECREMENT_REG
4294932228 PID:400002 TID:2a50002 Pulling 0 tx credits from the target
4294932228 PID:400002 TID:2a50002 HIFReadWrite:Enter
4294932228 PID:400002 TID:2a50002 Address 0x41b
4294932229 PID:400002 TID:2a50002 Byte mode (BlockLen: 1, BlockCount: 1)
4294932230 PID:400002 TID:2a50002 htcRegCompletion - Exit
4294932231 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294932233 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Sent 4 bytes [80000000]
4294932233 PID:400002 TID:36d0002 SDHC SendCommand: Cmd:0x35 Arg:0x90083001
4294932236 PID:400002 TID:2a50002 HIFReadWrite:Enter
4294932236 PID:400002 TID:2a50002 Address 0x472
4294932237 PID:400002 TID:2a50002 Byte mode (BlockLen: 1, BlockCount: 1)
4294932243 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294932243 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Sent 1 bytes [df]
4294932246 PID:400002 TID:36d0002 SDHC SendCommand: Cmd:0x35 Arg:0x90083601
4294932247 PID:400002 TID:2a50002 htcRegCompletion - Enter
4294932248 PID:400002 TID:2a50002 INT_STATUS_ENABLE: 0xdf
4294932248 PID:400002 TID:2a50002 htcRegCompletion - Exit
4294932252 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294932252 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Sent 1 bytes [1f]
4294932255 PID:400002 TID:36d0002 SDHC SendCommand: Cmd:0x35 Arg:0x90083601
4294932255 PID:400002 TID:2a50002 htcRegCompletion - Enter
4294932256 PID:400002 TID:2a50002 COUNTER_INT_STATUS_ENABLE: 0xff
4294932256 PID:400002 TID:2a50002 htcRegCompletion - Exit
4294932261 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294932261 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Sent 1 bytes [3f]
4294932264 PID:400002 TID:36d0002 SDHC SendCommand: Cmd:0x35 Arg:0x90083601
4294932264 PID:400002 TID:2a50002 htcRegCompletion - Enter
4294932265 PID:400002 TID:2a50002 COUNTER_INT_STATUS_ENABLE: 0xff
4294932265 PID:400002 TID:2a50002 htcRegCompletion - Exit
4294932270 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294932270 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Sent 1 bytes [7f]
4294932273 PID:400002 TID:36d0002 SDHC SendCommand: Cmd:0x35 Arg:0x90083601
4294932273 PID:400002 TID:2a50002 htcRegCompletion - Enter
4294932274 PID:400002 TID:2a50002 COUNTER_INT_STATUS_ENABLE: 0xff
4294932274 PID:400002 TID:2a50002 htcRegCompletion - Exit
4294932279 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294932279 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Sent 1 bytes [ff]
4294932282 PID:400002 TID:36d0002 SDHC SendCommand: Cmd:0x35 Arg:0x9008E401
4294932283 PID:400002 TID:2a50002 htcRegCompletion - Enter
4294932283 PID:400002 TID:2a50002 COUNTER_INT_STATUS_ENABLE: 0xff
4294932283 PID:400002 TID:2a50002 htcRegCompletion - Exit
4294932288 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294932288 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Sent 1 bytes [01]
4294932291 PID:400002 TID:2a50002 htcRegCompletion - Enter
4294932292 PID:400002 TID:2a50002 INT_WLAN: 0x1
4294932292 PID:400002 TID:2a50002 htcRegCompletion - Exit
4294932305 PID:400002 TID:5590012 HTCStart Exit
4294952306 PID:400002 TID:5590012 AR6K: ERROR - No WMI_READY event after 20000 ms, failing initialization

I suspect there is a bug in the SD host controller driver but cannot see
what it might be.

I have read previous discussions related to WMI_READY and I think the
card should be generating an interrupt at this point. The first
interrupt was handled by the host controller driver (log entry
4294928091) and was ack'd successfully (4294932179). I don't appear to
be getting a second interrupt.

Any ideas?

Many thanks,
Mike


Coordinator
Jul 28, 2009 at 1:43 AM

Mike,

There are some issues with Davinci host controller. I believe there is an errata that explains how SDIO interrupts need to be handled in the host controller driver. You might check that your HCD handles these per the errata.

Regards

Paul

Jul 28, 2009 at 1:35 PM

Hi Paul,

Thanks for the feedback. I have checked the errata and made a mod to the
HCD to sample the DAT1 signal (via SDIOST0) when unmasking the SDIO
interrupt to catch any missed interrupt. Also added logging of SDIOST0.
Still not seeing the mbox interrupt though, DAT1 line is high:

4294838504 PID:400002 TID:36d0002 SDHC SendCommand: Cmd:0x35 Arg:0x9008E401
4294838507 PID:400002 TID:2a50002 htcRegCompletion - Enter
4294838507 PID:400002 TID:2a50002 COUNTER_INT_STATUS_ENABLE: 0xff
4294838507 PID:400002 TID:2a50002 htcRegCompletion - Exit
4294838513 PID:400002 TID:36d0002 SDIO IRQ: CmdComplete, SDIOST0 0x3, SDIOIST 0x0, SDIOIEN 0x1
4294838513 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294838516 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Sent 1 bytes [01]
4294838516 PID:400002 TID:2a50002 htcRegCompletion - Enter
4294838517 PID:400002 TID:2a50002 INT_WLAN: 0x1
4294838517 PID:400002 TID:2a50002 htcRegCompletion - Exit
4294838522 PID:400002 TID:36d0002 SDIO IRQ: CmdComplete, SDIOST0 0x3, SDIOIST 0x0, SDIOIEN 0x1
4294838524 PID:400002 TID:56a0006 HTCStart Exit


I added a call to htcDSRHandler() to the end of HTCStart() to pull the
interrupt status from the card a couple of seconds after INT_WLAN is set:

4294840525 PID:400002 TID:56a0006 htcDsrHandler: Enter (target: 0xD1323F50
4294840525 PID:400002 TID:56a0006 HIFReadWrite:Enter
4294840528 PID:400002 TID:56a0006 Address 0x400
4294840528 PID:400002 TID:56a0006 Byte mode (BlockLen: 28, BlockCount: 1)
4294840531 PID:400002 TID:56a0006 Incremental 
4294840531 PID:400002 TID:56a0006 [Read ]
4294840534 PID:400002 TID:56a0006 Synchronous
4294840535 PID:400002 TID:56a0006 SDHC SendCommand: Cmd:0x35 Arg:0x1408001C
4294840537 PID:400002 TID:36d0002 SDIO IRQ: CmdComplete1, SDIOST0 0x3, SDIOIST 0x0, SDIOIEN 0x1
4294840537 PID:400002 TID:36d0002 SDHC GetCommandResponse: R5/R6 returned [3500100000]
4294840540 PID:400002 TID:36d0002 SDHC CommandCompleteHandler: Received 28 bytes [200004000e0000004400001100ee6e16b0823b01388096080000037f]
4294840542 PID:400002 TID:36d0002 SDIO IRQ: CmdComplete2, SDIOST0 0x3, SDIOIST 0x0, SDIOIEN 0x1
4294840544 PID:400002 TID:56a0006 
<------- Register Table -------->
4294840545 PID:400002 TID:56a0006 Int Status: 0x20
4294840546 PID:400002 TID:56a0006 CPU Int Status: 0x0
4294840548 PID:400002 TID:56a0006 Error Int Status: 0x4
4294840550 PID:400002 TID:56a0006 Counter Int Status: 0x0
4294840550 PID:400002 TID:56a0006 Mbox Frame: 0xe
4294840553 PID:400002 TID:56a0006 Rx Lookahead Valid: 0x0
4294840554 PID:400002 TID:56a0006 Rx Lookahead 0: 0x11000044
4294840555 PID:400002 TID:56a0006 Rx Lookahead 1: 0x166eee00
4294840558 PID:400002 TID:56a0006 Rx Lookahead 2: 0x13b82b0
4294840559 PID:400002 TID:56a0006 Rx Lookahead 3: 0x8968038
4294840560 PID:400002 TID:56a0006 Int Status Enable: 0x0
4294840562 PID:400002 TID:56a0006 Counter Int Status Enable: 0x7f
4294840564 PID:400002 TID:56a0006 <------------------------------->
4294840564 PID:400002 TID:56a0006 Valid interrupt source(s) in INT_STATUS: 0x20

This does not look right. I would expect "Int Status" to show a mailbox
interrupt (bits 0-3). Also, the Int Status Enable bytes do not look
correct. I think they should be 0xdf and 0xff at this stage.

Perhaps this points to an issue in the initialisation sequence? Or maybe an
issue in the HCD card write code?

Regards,
Mike

Coordinator
Jul 28, 2009 at 3:51 PM

Mike,

I sent you a PM.

 

Paul